Up to now, as an example of the parallelization method for generating the parallel program for the multicore microcomputer from the program for the single-core microcomputer, there is a parallelization compile method disclosed in Patent Literature 1.
In the parallelization compile method, after a sequential program for an embedded system to be executed by a single processor system has been divided into multiple macro tasks (hereinafter referred to as “MTs”), the MTs having a control dependency are conflated into one MT. Thereafter, in the paralielization compile method, parallelizable MTs are extracted on the basis of data dependency, and static scheduling is performed to generate a parallel program.
Patent Literature 1: JP2015-1807A corresponding to US2014372995(A1) and DE102014211047(A1)
The following describes related art which does not necessarily constitute prior art. In some single programs, multiple types of MTs are provided, and a combination of MT types to be executed varies according to condition. An example of such a single program is as follows. An MT of a first type and an MT of a third type are executed under one condition, and the MT of the first type and an MT of a second type are executed under another condition. Specifically, the single program includes multiple processing patterns which are different in the combination of MT types, and the MTs of the types included in the processing pattern corresponding to the condition are executed. In this single program, the MTs of all types are not included in each processing pattern.
When there is conditional branch processing in the single program, the method disclosed in Patent Literature 1 cannot recognize how branching will occur during actual program execution. Hence, in the parallel program generated in Patent Literature 1, an MT that is not actually executed under a certain condition when the cores of the multicore microcomputer execute the MTs may be allocated to the core. For that reason, the core does not execute the allocated MT in some cases and the method disclosed in Patent Literature 1 generates such parallel programs that multicore microcomputer efficiency is reduced.